An Electrical Fast Transient (EFT)/Burst events occurs when Inductive loads such as relays, switch contactors, or heavy-duty motors produce bursts of narrow high-frequency transients on the power distribution system when de-energized. These fast transients can also be produced when the utility provider switches their power factor correction equipment in or out. Also, a common cause of power line transients is sparking that occurs whenever an AC power cord is plugged in, equipment is switched off, or when circuit breakers are opened or closed. The schematic below shows how transients from these events are generated and are coupled to end equipment over power lines. IEC 61000-4-4 is an IEC standard designed to test fast transient or burst immunity of a electronic subsystem. Typical systems are required to be operationally immune to EFT are networking systems, and other industrial applications.
The picture below shows typical EFT test equipment and test equipment setup. The EFT immunity test setup for IO's (integrated circuit input and output pins) is shown in the below schematic. A burst signal from a burst generator is fed through a test cable which is adjacent to a data cable connected to a DUT (Device Under Test). For Power ports, the stress burst generator pulse is coupled to the DUT's power signals or to PCB power traces connecting to the DUT.
IEC61000-4-4 specifies the magnitude of the stress burst level pulses and their duration. This can be seen in the below picture.
For further information on EFT/Burst stress procedures see:
The characteristic of the EFT stress waveform looks as in the below picture:
How To Diagnose and Solve EFT/Burst ESD Failures
EFT ESD failures are caused when the energy of a EFT/Burst stress (transient induced) pulse corrupts data transmitted or power supply levels during normal operation of an application. TVS (Transient Voltage Suppressor) diodes are designed to suppress transient voltage pulses being impressed on power or data traces in an application and will be able to suppress not only ESD and surge events, but also EFT/Burst events. The same rules for PCB placement for these diodes apply as for protection for an IEC stress event.
Key Factors in Understanding EFT/Burst ESD failures
As can be seen in the below picture, the transient-induced noise, as a result of a EFT/Burst stress event, is both common mode and differential mode noise. Common-mode noise is present or "common"� to both conductors and is typically “in phase” within the conductors. Differential noise is present on only one conductor or present in opposite phase in both conductors.
Transient induced signals as a result of a EFT-Burst stress pulse can effect multiple different embedded processor functions by disturbing the valid flow in the processors communication with other internal or external to PCB integrated circuits or displays. The following processor functional elements can be affected:
Problem
1: Power/Ground Signals: Negative glitches induced on power signals can cause brownout condition if duration of negative supply glitch is long enough for system digital or analog stages to loose their state or signal magnitude. Positive signals induced on supply signals could cause supply clamps in ESD circuits to fire causing supply clamping and much supply current to flow, or a condition is created where latch/hold conditions of a parasitic scr can be sufficient to cause latch-up behavior with a corresponding high current flows in the supply of the processor.
HOW TO FIX
A: PCB power signal routing is very critical and must always make certain that decoupling/bypass capacitors are placed such that the integrated circuit will always directly see the effect of these filters - this means that decoupling/bypass capacitors need to be connected to their respective power planes as close as possible to the primary power supply connection of an integrated circuit. Never expect decoupling/bypass capacitors to do the job of filtering EFT/Burst induced glitches for the power supply of an integrated circuit when their PCB placement location is far away from the supply pins of an integrated circuit.
B: At the point on the PCB where the power supply enters into the PCB system, always use power entry filters made up of TVS diodes, ferrite beads, bypass/bulk capacitors, and common mode chokes. Always use filter/decoupling capacitors and inductors to suppress EFT/Burst stresses as close as possible to the power pin of an integrated circuit.
Problem
1: Reset, clock, analog, edge sensitive triggers, high frequency, and various communication signals are all susceptible to positive or negative glitches induced by EFT/Burst stresses. It is very common that high impedance reset or similar inputs to integrated circuits are susceptible to glitches resulting from EFT/Busts stresses. These glitches may either appear on the power and or ground traces or appear on the control signals feeding into the PCB circuitry that generates the integrated circuits reset pulse .
HOW TO FIX
A: Reset inputs to integrated circuits are typically high impedance inputs and are susceptible to system noise generated by EFT/Burst stresses. Integrated circuits operation may get disturbed by a reset "glitch" resulting from a EFT/Burst stress event. Care must be taken to add filtering capacitors and pullups/pulldowns (depending on the reset's pin's active state) to the reset signal as close as possible to the integrated circuit.
B: Similar filtering structures need to be added to I2c pins.
C: UART pins require TVS diodes at the UART connector.
D: Care must be taken that the system ground of a RS232 connector is protected with a TVS diode.
More information about EFT/Burst stress voltages and EFT/Burst stress procedures is given at:
Link to other ESD and latch Up topics:
- Human Body Model (HBM) Charged Device Model (CDM) Machine Model (MM) System Level ESD - IEC 61000-4-2 Lightning/Surge - IEC 61000-4-5 Automotive ESD - AEC Q100 and ISO 10605 Latch-Up Electrical Overstress (EOS) ESD and Latch Up Testing and Qualification Procedures
For immediate consulting help on the above topics, contact (blog with) ESD Unlimited LLC staff at the
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